An embodiment of an electronic device as is set forth in the opening paragraph is known from U.S. Pat. No. 4,679,299. The known electronic device constitutes a self-aligned three-dimensionally integrated circuit having two channel regions responsive to a common gate electrode. The known electronic device operates based on a stacked CMOS field effect transistor device wherein a pair of self-aligned field transistors, utilizing a common gate electrode, exhibit minimum source/drain coupling between suitable stack devices and which provide a relatively planar surface topology.
In the known electronic device, multiple semiconductor layers are deposited for structuring the stack. First, suitably doped regions are formed in a silicon substrate layer forming drain and source electrodes of a first Thin Film Transistor (TFT). After this, a layer of dielectric material is deposited for electrically isolating the source and drain electrodes from a gate electrode, after which a second layer of dielectric material is deposited for isolating the gate electrode from the channel. The first TFT forms a lower component of the known electronic device. When the components of the first TFT are formed, a second TFT sharing the gate electrode with the first TFT is formed on top of the first TFT. The second TFT comprises a suitable plurality of dielectric layers for forming source and drain electrodes of the second TFT.
It is a disadvantage of the known electronic device that a plurality of processing steps is necessary for depositing and patterning different layers of materials, notably different layers of dielectric materials.